The present invention relates in general to electronic devices and, in more particular, to techniques effectively applicable to electronic devices having power transistors.
Electronic devices include a power module for control of overcharging or overdischarging of a lithium (Li) ion secondary battery unit as built in small size electronic equipment such as portable telephone handsets, handheld information processing terminal equipment, and mobile personal computers or the like. This power module is accommodated within a case housing along with more than one Li-ion secondary battery.
The power module is typically designed so that chosen parts or components are mounted on a wiring substrate, which include power transistors, a semiconductor device for use as a controller, resistive elements, capacitive elements and others.
The power transistors widely employable therein may include power transistors with a plastic package structure of the surface mount type, generally called the TSSOP (Thin Shrink Small Out-line Package) type, for example.
A currently available power transistor of the TSSOP type is mainly constituted from a semiconductor chip having an element formation surface and a back surface on each of which electrodes are formed, a support body for supporting the back surface of the semiconductor chip, a resin sealing body for sealing the semiconductor chip, and a plurality of electrical leads. A respective one of the plurality of leads is designed to extend inwardly and outwardly of the resin seal body and have an internal lead portion (also referred to as inner lead) that is positioned inside of the resin seal body and an external lead portion (also called outer leads) placed outside of the resin seal body. Respective external lead portions of the plurality of leads are machined so that these are bent and fold into a gull wing-like shape, which is one of known surface-mount lead shapes. The plurality of leads include more than one lead having its internal lead portion that is electrically connected via a conductive wire to an electrode on the element formation surface of the semiconductor chip while letting internal lead portions of the remaining leads be electrically connected via the support body to those electrodes on the back surface of the semiconductor chip.
Note here that the power module per se has been disclosed, for example, in Hitachi Microcomputer Technical Bulletin, Vol. 11, No. 2 at pp. 33-35.
Also note that one typical power transistor of the TSSOP type is recited for example in xe2x80x9c2.5-V Driven Trench Gate MOSFET of Third Generation,xe2x80x9d Toshiba Review, Vol. 53, No. 11 (1998) at pp. 45-47.
The inventors as named herein have analyzed the above-stated power module to find out problems which follow.
With miniaturization or xe2x80x9cdownsizingxe2x80x9d of small size electronic equipment, power modules as built in the small size electronic equipment have decreased in dimension accordingly. As the quest for downsizing of such small size electronic equipment is expected to grow endlessly in near future, a need is felt to further downsize the power modules. To achieve such downsizing of the power module, it should be required to reduce or shrink the area of a wiring substrate used. Area shrinkage of the wiring substrate would result in a decrease in contact area between the wiring substrate and its outside air, which in turn makes it difficult for the heat transmitted from power transistors to the wiring substrate to escape outwardly thus causing the power module to decrease in heat releasability. If the power transistors are designed to increase in heat releasability then it becomes possible to compensate for any possible decreases in heat releasability of such power modules which can occur due to shrinkage of the wiring substrate area. Unfortunately, in those package structures that are inherently designed to employ a resin seal body for sealing a semiconductor chip and internal lead portions of leads associated therewith, such as the TSSOP type one, it is impossible to successfully compensate for the heat releasability of power transistors otherwise occurring due to shrinkage in area of the wiring substrate because of the fact that the semiconductor chip and the internal lead portions of the leads are entirely covered with resin materials that are less in heat conductivity. This in turn makes it difficult to further downsize the power module.
It is therefore an object of the present invention to provide a technique for enabling miniaturization or downsizing of an electronic device.
This and other objects and new features of the present invention will become apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
A representative one of the inventive concepts as disclosed and claimed herein will be explained in brief below.
An electronic device comprises a wiring substrate having on its principal surface a plurality of electrodes along with a first semiconductor device and a second semiconductor device which are built on the principal surface of the wiring substrate, which device is featured in that
said first semiconductor device includes:
a semiconductor chip having a first principal surface and a second principal surface that oppose each other, first and second electrodes as formed on said first principal surface, and a third electrode formed on said second principal surface;
a first lead having a first portion placed over said first electrode and a second portion as integrally formed with said first portion and positioned outside of said semiconductor chip;
a second lead having a first portion placed over aid second electrode and a second portion as integrally formed with said first portion and positioned outside of said semiconductor chip;
a plurality of projected electrodes as disposed between said first lead and said first electrode and between said second lead and said second electrode for electrically connecting between respective ones of them; and
an insulative sheet disposed between said first lead and the first principal surface of said semiconductor chip and between said second lead and said semiconductor chip, which sheet covers a selected area of the first principal surface of said semiconductor chip other than a region in which said plurality of projected electrodes are disposed, wherein
the second portion of each of said first lead and said second leads is bent so that its distal end is disposed at substantially the same height as that of the second principal surface of said semiconductor chip in a direction along the thickness of said semiconductor chip, and
a respective one of the distal end of the second portion of each of said first lead and second lead and said third electrode is connected to its corresponding one of electrodes of said wiring substrate.